The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Apr. 08, 2019
Methods of fabricating silicon-on-insulator (soi) semiconductor devices using blanket fusion bonding
Applicant:
Kulite Semiconductor Products, Inc., Leonia, NJ (US);
Inventors:
Alexander A. Ned, Kinnelon, NJ (US);
Sorin Stefanescu, New Milford, NJ (US);
Joseph R. VanDeWeert, Maywood, NJ (US);
Assignee:
Kulite Semiconductor Products, Inc., Leonia, NJ (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 27/146 (2006.01); H01L 31/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76256 (2013.01); H01L 21/7624 (2013.01); H01L 21/76251 (2013.01); H01L 27/1203 (2013.01); H01L 27/14687 (2013.01); H01L 24/80 (2013.01); H01L 31/1892 (2013.01); H01L 2221/68363 (2013.01); H01L 2224/80896 (2013.01);
Abstract
A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.