The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Aug. 29, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Naofumi Abiko, Kawasaki Kanagawa, JP;

Masahiro Yoshihara, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/24 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/08 (2013.01); G11C 7/1063 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract

According to one embodiment, a semiconductor storage device includes a memory cell and a memory cell connected to a word line, a first bit line BL connected to the memory cell, a second bit line BL connected to the memory cell, and a control circuit. The control circuit includes a first transistor provided between the first bit line and the node and including one end electrically connected to the node, and a second transistor provided between the second bit line and the node and including one end electrically connected to the node; the second transistor is provided adjacent to the first transistor; and the control circuit is configured to set one of the first transistor and the second transistor in an ON state while setting the other in an OFF state.


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