The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Mar. 31, 2015
Applicant:

Xpliant, San Jose, CA (US);

Inventors:

Premshanth Theivendran, Foster City, CA (US);

Weihuang Wang, Los Gatos, CA (US);

Guy Hutchison, Santa Clara, CA (US);

Gerald Schmidt, San Jose, CA (US);

Assignee:

Marvell Asia Pte, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/33 (2020.01); G06F 30/30 (2020.01); G06F 30/327 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/30 (2020.01); G06F 30/327 (2020.01);
Abstract

Systems and methods for generating an RTL description based on logical signal groupings are described. Logical interfaces are declared in a compressed form, and logical signal grouping is defined in a markup document. The definitions from the markup document are used by expansion scripts to populate RTL modules and encapsulate block connectivity and functionality. Multiple interfaces can be created instantly, and interface definitions for common interfaces may be easily re-defined. Default values may be assigned to module outputs for testing purposes, allowing for multi-module simulations where certain modules are shelled-out.


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