The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Dec. 25, 2018
Applicant:

C-sky Microsystems Co., Ltd., Hangzhou, Zhejiang, CN;

Inventors:

Aiyong Ma, Hangzhou, CN;

Bo Sun, Hangzhou, CN;

Baolin Xia, Hangzhou, CN;

Xianshao Chen, Hangzhou, CN;

Assignee:

C-SKY Microsystems Co., Ltd., Hangzhou, Zhejiang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/38 (2006.01); G06F 13/36 (2006.01); G06F 13/362 (2006.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/362 (2013.01); G06F 13/1668 (2013.01);
Abstract

Provided is a bitwise writing apparatus for a SOC system. The apparatus includes a slave device interface module, a decoding module and a master device interface module. The slave device interface module is configured to receive a write request sent by a master device interface of a bus controller and send the write request to the decoding module. The decoding module is configured to receive the write request sent by the slave device interface module, decode the write request and send valid information after the decoding to the master device interface module. The master device interface module is configured to receive the valid information sent by the decoding module, read data in a destination address, perform a bitwise operation for the read data to obtain new data, send a write request to a slave device interface of the bus controller and write the obtained new data into a peripheral register corresponding to the destination address. The system can effectively reduce the instruction storage space and thereby reduce the chip area and lower the chip cost.


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