The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
May. 15, 2018
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 3/06 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G11C 7/10 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 13/1673 (2013.01); G11C 7/22 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G06F 13/1668 (2013.01); G11C 5/04 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01);
Abstract
A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.