The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Feb. 12, 2018
Applicant:

Tata Consultancy Services Limited, Mumbai, IN;

Inventors:

Ajay Kattepur, Bangalore, IN;

Hemant Kumar Rath, Bangalore, IN;

Anantha Simha, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); H04L 12/24 (2006.01); H04L 29/08 (2006.01); G06F 11/34 (2006.01); H04W 4/70 (2018.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5072 (2013.01); G06F 11/3428 (2013.01); G06F 11/3442 (2013.01); G06F 11/3466 (2013.01); H04L 41/0823 (2013.01); H04L 67/10 (2013.01); H04L 67/12 (2013.01); H04W 4/70 (2018.02); G06F 11/3062 (2013.01); G06F 11/3419 (2013.01); G06F 2201/865 (2013.01); G06F 2201/88 (2013.01);
Abstract

In order to make use of computational resources available at runtime through fog networked robotics paradigm, it is critical to estimate average performance capacities of deployment hardware that is generally heterogeneous. It is also not feasible to replicate runtime deployment framework, collected sensor data and realistic offloading conditions for robotic environments. In accordance with an embodiment of the present disclosure, computational algorithms are dynamically profiled on a development testbed, combined with benchmarking techniques to estimate compute times over the deployment hardware. Estimation in accordance with the present disclosure is based both on Gustafson's law as well as embedded processor benchmarks. Systems and methods of the present disclosure realistically capture parallel processing, cache capacities and differing processing times across hardware.


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