The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Sep. 28, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Hiroshi Furukawa, Yokohama, JP;

Ichiro Kasama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/78 (2006.01); G06F 12/02 (2006.01); G06F 9/34 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30145 (2013.01); G06F 9/34 (2013.01); G06F 9/3879 (2013.01); G06F 9/3897 (2013.01); G06F 12/02 (2013.01); G06F 15/7867 (2013.01); G06F 2212/1021 (2013.01);
Abstract

A reconfigurable arithmetic device includes a plurality of processor elements configured to perform first arithmetic processes corresponding to a first type of instruction and second arithmetic processes corresponding to a second type of instruction, a random-access memory (RAM), and a control unit. The first type of instruction is written into the RAM at a first address, data for the first type of instruction is written into the RAM at a second address, and data for the second type of instruction is written into the RAM at a third address. When the first type of instruction is written at the first address, the control unit decodes the first type of instruction and configures the processor elements to perform the first arithmetic processes. When data for the second type of instruction is written at the third address, the control unit configures the processor elements to perform the second arithmetic processes.


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