The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Feb. 27, 2018
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Tadashi Morita, Kanagawa, JP;

Masahiko Hashimoto, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 15/04 (2006.01); G01S 15/50 (2006.01); G01S 15/32 (2006.01); G01S 15/931 (2020.01); G01S 7/536 (2006.01); G01S 7/534 (2006.01); G01S 7/53 (2006.01);
U.S. Cl.
CPC ...
G01S 15/04 (2013.01); G01S 7/536 (2013.01); G01S 15/325 (2013.01); G01S 15/50 (2013.01); G01S 15/931 (2013.01); G01S 7/53 (2013.01); G01S 7/534 (2013.01);
Abstract

A detection apparatus that includes correlation processing systems that each find a correlation between a predetermined code sequence and a wave detection signal obtained by detecting a phase-modulated input wave at a frequency different from a frequency used by a different one of the correlation processing systems, and thereby generate a correlation signal, level reduction processors that each receive the correlation signal from a corresponding one of the plurality of correlation processing systems and reduce a level of the received correlation signal when the correlation signal is not to be used for detection of the target or do not reduce the level of the received correlation signal when the correlation signal is to be used for detection of the target, and a detector that detects at least presence or absence of the target based on the correlation signal processed by each of the plurality of level reduction processors.


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