The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Nov. 05, 2018
Xilinx, Inc., San Jose, CA (US);
Lik Huay Lim, Singapore, SG;
Andy Widjaja, Singapore, SG;
King Yon Lew, Singapore, SG;
Mohsen H. Mardi, Saratoga, CA (US);
Xuejing Che, Singapore, SG;
XILINX, INC., San Jose, CA (US);
Abstract
A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.