The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Dec. 09, 2015
Applicant:

Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Srihari V. Angaluri, Raleigh, NC (US);

Gary D. Cudak, Wake Forest, NC (US);

Ajay Dholakia, Cary, NC (US);

Chulho Kim, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01); G06F 1/20 (2006.01); G06F 1/3228 (2019.01); G06F 1/3215 (2019.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
H04L 43/0882 (2013.01); G06F 1/206 (2013.01); G06F 1/3215 (2013.01); G06F 1/3228 (2013.01); G06F 9/4893 (2013.01); G06F 9/505 (2013.01); G06F 9/5077 (2013.01); H04L 43/0817 (2013.01); H04L 43/16 (2013.01); G06F 2209/504 (2013.01); G06F 2209/508 (2013.01); G06F 2209/5019 (2013.01); G06F 2209/5022 (2013.01); Y02D 10/16 (2018.01); Y02D 10/22 (2018.01); Y02D 10/24 (2018.01); Y02D 10/36 (2018.01);
Abstract

A method includes obtaining component utilization data for multiple components of a compute node during at least one previous execution of a workload. The method further includes using the component utilization data to identify a first component having a utilization level that is less than a threshold utilization level during the at least one previous execution of the workload, wherein the first component is one of the multiple components of the compute node. The method still further includes, during a subsequent execution of the workload on the compute node, throttling the first component to prevent the first component from exceeding the threshold utilization level.


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