The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Oct. 07, 2019
Applicant:

Denso Corporation, Kariya, Aichi-pref., JP;

Inventors:

Kunihiko Nakamura, Kariya, JP;

Tomohiro Nezuka, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/36 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0678 (2013.01); H03M 1/1245 (2013.01); H03M 1/365 (2013.01);
Abstract

A ΔΣ modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.


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