The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Nov. 26, 2019
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Hsi-En Liu, Kaohsiung, TW;

Shawn Min, Hsinchu County, TW;

You-Jyun Peng, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/08 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0893 (2013.01); H03L 7/0895 (2013.01); H03L 7/099 (2013.01);
Abstract

The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.


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