The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Oct. 17, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Joung Won Park, San Diego, CA (US);

Bo Sun, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/04 (2006.01); H03G 3/30 (2006.01); H01L 23/66 (2006.01); H01L 25/18 (2006.01); H03F 1/02 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03G 3/3042 (2013.01); H01L 23/66 (2013.01); H01L 25/18 (2013.01); H03F 1/0205 (2013.01); H03F 3/45183 (2013.01); H04B 1/0475 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6655 (2013.01); H03F 2200/222 (2013.01); H03F 2200/267 (2013.01); H03F 2200/301 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45178 (2013.01); H03F 2203/45201 (2013.01); H03G 2201/103 (2013.01); H04B 2001/0416 (2013.01);
Abstract

In certain aspects, an amplifier includes a first transistor including a gate, a drain, and a source, wherein the gate of the first transistor is coupled to a first input of the amplifier. The amplifier also includes a second transistor including a gate, a drain, and a source, wherein the gate of the second transistor is coupled to a second input of the amplifier. The amplifier further includes a first signal path coupled between the first input of the amplifier and the source of the second transistor, a second signal path coupled between the second input of the amplifier and the source of the first transistor, a first load coupled to the drain of the first transistor, and a second load coupled to the drain of the second transistor.


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