The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2020
Filed:
Jul. 05, 2019
Fuji Electric Co., Ltd., Kanagawa, JP;
Keishirou Kumada, Nagano, JP;
Yasuyuki Hoshi, Nagano, JP;
Yoshihisa Suzuki, Nagano, JP;
Yuichi Hashizume, Nagano, JP;
FUJI ELECTRIC CO., LTD., Kanagawa, JP;
Abstract
In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an nstarting substrate, an ndrift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No nsource region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.