The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Apr. 16, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Sung-Min Hwang, Hwasung-si, KR;

Dong-Sik Lee, Hwasung-si, KR;

Joon-Sung Lim, Hwasung-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 23/532 (2006.01); H01L 27/11573 (2017.01); H01L 29/06 (2006.01); H01L 27/11526 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11286 (2013.01); H01L 23/53295 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 29/0649 (2013.01);
Abstract

A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.


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