The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Nov. 24, 2017
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Seiji Muraoka, Sakai, JP;

Yukio Shimizu, Sakai, JP;

Motoji Shiota, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 23/00 (2006.01); G02F 1/1345 (2006.01); G09F 9/30 (2006.01); G09F 9/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); G02F 1/1345 (2013.01); G02F 1/13458 (2013.01); G09F 9/00 (2013.01); G09F 9/30 (2013.01); H01L 24/11 (2013.01); H01L 2224/06 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73203 (2013.01);
Abstract

Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first lineis disposed so as to pass under an adjacent second line, or a second lineis disposed so as to pass over an adjacent first line. In this case, three lines are disposed in any area between padsin each stage such that the three lines include a first linesituated in the middle, and second linesare situated so as to have the first linepositioned therebetween. Thus, the pitch between the padscan be further reduced without reducing the width of the pads


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