The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Nov. 12, 2019
Applicant:

Fairchild Semiconductor Corporation, Phoenix, AZ (US);

Inventors:

Aira Lourdes Villamor, Lapu-Lapu, PH;

Erwin Victor Cruz, Koronadal, PH;

Geraldine Suico, Consolacion, PH;

Silnore Sabando, Lapu-Lapu, PH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/495 (2006.01); H01L 23/492 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49544 (2013.01); H01L 21/4821 (2013.01); H01L 21/4842 (2013.01); H01L 21/561 (2013.01); H01L 23/3157 (2013.01); H01L 23/492 (2013.01); H01L 23/4952 (2013.01); H01L 23/49548 (2013.01); H01L 23/49575 (2013.01); H01L 23/49582 (2013.01); H01L 23/3107 (2013.01);
Abstract

In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove. The method can further include separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure.


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