The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Feb. 11, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Takashi Shirono, Yokkaichi Mie, JP;

Eiji Takano, Nagoya Aichi, JP;

Gen Toyota, Yokkaichi Mie, JP;

Eiichi Shin, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/304 (2013.01); H01L 21/30625 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.


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