The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Feb. 15, 2017
Applicant:

Centec Networks (Su Zhou) Co., Ltd., Suzhou, CN;

Inventors:

Jun Xu, Suzhou, CN;

Zhen Jiang, Suzhou, CN;

Xiaoyang Zheng, Suzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G06F 9/30 (2018.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 9/30029 (2013.01); G06F 13/00 (2013.01); G11C 7/1015 (2013.01); G11C 7/14 (2013.01); G11C 7/22 (2013.01); Y02D 10/14 (2018.01);
Abstract

The present invention discloses a data processing method and system for a scalable multi-port memory. The multi-port memory is a 2-read n-write multi-port memory unit. The method comprises: assembling two 2R1W memories into one Bank memory unit; assembling n/2 Bank memory units in depth into a hardware architecture of one 2-read n-write multi-port memory unit; under one clock cycle, when data is written into the 2-read n-write multi-port memory unit, if the size of the data is less than or equal to the bit width of the 2R1W memory, writing the data into different 2R1W memories respectively; and if the size of the data is greater than the bit width of the 2R1W memory, waiting for a second clock cycle, and when the second clock cycle comes, writing the high and low bits of the written data into the two 2R1W memories of one Bank memory unit respectively.


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