The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Nov. 14, 2018
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Akira Tagawa, Sakai, JP;

Takuya Watanabe, Sakai, JP;

Yasuaki Iwase, Sakai, JP;

Takatsugu Kusumi, Sakai, JP;

Yohei Takeuchi, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G06F 3/0412 (2013.01); G06F 3/0416 (2013.01); G11C 19/28 (2013.01); G09G 2310/0286 (2013.01);
Abstract

Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.


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