The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Dec. 19, 2018
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Kyung-Rok Kim, Osan-si, KR;

Taegung Kim, Osan-si, KR;

Haejin Park, Osan-si, KR;

EunJi Park, Osan-si, KR;

Kimin Son, Osan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/32 (2016.01); G09G 3/3275 (2016.01); G06F 3/044 (2006.01); H01L 27/32 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G06F 3/044 (2013.01); G06F 3/0412 (2013.01); G06F 3/0446 (2019.05); G06F 3/04164 (2019.05); G06F 3/04166 (2019.05); G09G 3/32 (2013.01); G09G 3/3275 (2013.01); H01L 27/323 (2013.01); H01L 27/3255 (2013.01); H01L 27/3276 (2013.01); G09G 2310/027 (2013.01); G09G 2310/06 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); H01L 27/322 (2013.01); H01L 27/3272 (2013.01);
Abstract

The display apparatus may include gate lines passing through a display area of a substrate, data lines passing through the display area of the substrate, pixel driving power lines passing through the display area of the substrate, a plurality of pixels having a pixel driving chip mounted on at least one pixel area defined on the substrate and connected and connected to an adjacent gate line and data line and a light emission part connected to the pixel driving chip, a gate driving chip array part mounted in a non-display area of the substrate and connected to the gate lines, and a data driving chip array part mounted in the non-display area of the substrate and connected to the data lines.


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