The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2020
Filed:
Jul. 07, 2017
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Naya Ha, Seoul, KR;
Yong-Durk Kim, Hwaseong-si, KR;
Bong-hyun Lee, Suwon-si, KR;
Hyung-ock Kim, Seoul, KR;
Kwang-ok Jeong, Hwaseong-si, KR;
Jae-hoon Kim, Seoul, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 119/06 (2020.01); G06F 119/10 (2020.01); G06F 119/12 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/10 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01);
Abstract
A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.