The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2020
Filed:
Sep. 30, 2019
Applicant:
Erik Debenedictis, Albuquerque, NM (US);
Inventor:
Erik DeBenedictis, Albuquerque, NM (US);
Assignee:
ZETTAFLOPS LLC, Albuquerque, NM (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/82 (2006.01); H03H 11/34 (2006.01); H03K 17/92 (2006.01); G11C 11/418 (2006.01); G11C 11/412 (2006.01); G06N 10/00 (2019.01); H03K 19/195 (2006.01); H01L 39/22 (2006.01);
U.S. Cl.
CPC ...
G06F 15/82 (2013.01); G06N 10/00 (2019.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); H03H 11/34 (2013.01); H03K 17/92 (2013.01); H03K 19/195 (2013.01); H01L 39/223 (2013.01); H01L 39/228 (2013.01);
Abstract
A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.