The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2020
Filed:
Mar. 13, 2017
Sharp Kabushiki Kaisha, Sakai, Osaka, JP;
Tetsuo Kikuchi, Sakai, JP;
Tohru Daitoh, Sakai, JP;
Hajime Imai, Sakai, JP;
Toshikatsu Itoh, Sakai, JP;
Hisao Ochi, Sakai, JP;
Hideki Kitagawa, Sakai, JP;
Masahiko Suzuki, Sakai, JP;
Teruyuki Ueda, Sakai, JP;
Ryosuke Gunji, Sakai, JP;
Kengo Hara, Sakai, JP;
Setsuji Nishimiya, Sakai, JP;
SHARP KABUSHIKI KAISHA, Sakai, JP;
Abstract
Provided is an active matrix substrate provided with a substrate (), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (), a plurality of second oxide semiconductor TFTs () disposed in a display area, and a first inorganic insulating layer () covering the plurality of second oxide semiconductor TFTs (), the first oxide semiconductor TFT () having a lower gate electrode (A), a gate insulating layer (), an oxide semiconductor (A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (A) and a drain electrode (A), and an upper gate electrode (BG) disposed on the oxide semiconductor (A) with an insulating layer that includes the first inorganic insulating layer () interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer () covering the first oxide semiconductor TFT ().