The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Jun. 27, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Ramamurthy Vishweshwara, Bengaluru, IN;

Pramod Kumar Baskar, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/34 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01); H03M 1/66 (2006.01); H03M 1/36 (2006.01); G05F 3/02 (2006.01);
U.S. Cl.
CPC ...
H03M 1/462 (2013.01); H03M 1/1245 (2013.01); H03M 1/466 (2013.01); G05F 3/02 (2013.01); H03M 1/12 (2013.01); H03M 1/365 (2013.01); H03M 1/66 (2013.01);
Abstract

An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.


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