The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Mar. 27, 2018
Applicant:

Ablic Inc., Chiba-shi, Chiba, JP;

Inventors:

Mitsuhiro Yoshimura, Chiba, JP;

Masahiro Hatakenaka, Chiba, JP;

Assignee:

ABLIC INC., Chiba, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/417 (2013.01); H01L 29/41766 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7396 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a base region formed in the semiconductor substrate; a trench formed from the first surface and the second surface into the semiconductor substrate; a gate insulating film covering an inner side of the trench; a gate electrode embedded to a third height; an insulating film formed on the gate electrode; a first region which has the first surface and in which a base contact region is formed; and a second region which has the second surface and in which a source region is formed, the first region and the second region being alternately arranged in the trench extension direction to prevent a reduction in channel formation density.


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