The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2020
Filed:
Aug. 22, 2018
Xilinx, Inc., San Jose, CA (US);
James Karp, Saratoga, CA (US);
Michael J. Hart, Palo Alto, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.