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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10811432 B1

PDFFull Text
Date of Patent:
Oct. 20, 2020

Filed:

Oct. 08, 2018

Semiconductor device and method of manufacturing the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Nobuo Tsuboi, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Fernando L Toledo

Assistant Examiner:

Neil R Prasad

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 21/033 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/0337 (2013.01); H01L 21/76283 (2013.01); H01L 21/76832 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0928 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01); H01L 29/78 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 27/088 (2013.01); H01L 27/0922 (2013.01);
Abstract

There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.

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