The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

May. 07, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Kwang Ok Jeong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/552 (2006.01); H01L 23/544 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/3128 (2013.01); H01L 23/5223 (2013.01); H01L 23/5283 (2013.01); H01L 23/544 (2013.01); H01L 23/552 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/16 (2013.01); H01L 28/40 (2013.01); H01L 2223/54433 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; a first encapsulant covering at least a portion of each of the inactive surface and side surfaces of the semiconductor chip, and having one or more recessed portions recessed towards the inactive surface of the semiconductor chip; a metal layer disposed on the first encapsulant, and filling at least a portion of each of the recessed portions; and an interconnect structure disposed on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad. A surface of the metal layer in contact with the first encapsulant has a surface roughness greater than a surface roughness of a surface of the metal layer spaced apart from the first encapsulant.


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