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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10811329 B1

PDFFull Text
Date of Patent:
Oct. 20, 2020

Filed:

Feb. 10, 2016

Ceramic substrate and method for producing a ceramic substrate

Applicant:

Koninklijke Philips N.v., Eindhoven, NL;

Inventors:

Peter Luerkens, Aachen, DE;

Albert Garcia Tormo, Eindhoven, NL;

Ulf Mueter, Hamburg, DE;

Assignee:

KONINKLIJKE PHILIPS N.V., Eindhoven, NL;

Attorney:

Larry Liberchuk

Primary Examiner:

Hung K Vu

Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); H01L 23/50 (2006.01); H01L 25/07 (2006.01); C04B 35/10 (2006.01); C04B 35/457 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/15 (2013.01); C04B 35/10 (2013.01); C04B 35/457 (2013.01); H01L 23/49811 (2013.01); H01L 23/50 (2013.01); H01L 25/072 (2013.01); H01L 27/0805 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19106 (2013.01);
Abstract

The present invention relates to a ceramic substrate () comprising: a front side (-), which comprises: i) a power semiconductor (--); and ii) a first metallic layer () comprising at least one first metallic plane contact (--), which is configured to connect the power semiconductor (--) to a first terminal (--) on an edge (-) of the ceramic substrate (); a back side (-), which comprises: i) a capacitor () which is attached to a ii) second metallic layer () comprising at least one second metallic plane contact (--), which is configured to connect the capacitor () to a second terminal (--) on the edge (-) of the ceramic substrate (); and a metallic frame (), which is configured to connect the first metallic layer () to the second metallic layer ().

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