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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10811281 B1

PDFFull Text
Date of Patent:
Oct. 20, 2020

Filed:

Jun. 26, 2019

Manufacturing method of semiconductor device and semiconductor device

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shoji Hashizume, Takasaki, JP;

Keita Takada, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McGinn IP Law Group, PLLC

Primary Examiner:

Hrayr A Sayadian

Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/544 (2006.01); B29C 45/14 (2006.01); B29C 45/00 (2006.01); H01L 23/31 (2006.01); B29L 31/34 (2006.01); H02P 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); B29C 45/0025 (2013.01); B29C 45/0046 (2013.01); B29C 45/14336 (2013.01); B29C 45/14655 (2013.01); H01L 21/4825 (2013.01); H01L 21/4842 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49513 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/544 (2013.01); B29C 2045/0027 (2013.01); B29L 2031/34 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54433 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/181 (2013.01); H02P 27/06 (2013.01);
Abstract

A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.

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