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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10811260 B1

PDFFull Text
Date of Patent:
Oct. 20, 2020

Filed:

Apr. 12, 2019

Semiconductor device having buried gate structure and method for fabricating the same

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Tae-Su Jang, Gyeonggi-do, KR;

Jin-Chul Park, Gyeonggi-do, KR;

Ji-Hwan Park, Chungcheongbuk-do, KR;

Il-Sik Jang, Gyeonggi-do, KR;

Seong-Wan Ryu, Gyeonggi-do, KR;

Se-In Kwon, Incheon, KR;

Jung-Ho Shin, Seoul, KR;

Dae-Jin Ham, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T Group LLP

Primary Examiner:

Hrayr A Sayadian

Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/24 (2006.01); H01L 29/78 (2006.01); H01L 27/22 (2006.01); H01L 29/66 (2006.01); H01L 43/12 (2006.01); H01L 45/00 (2006.01); H01L 27/108 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 27/228 (2013.01); H01L 27/2454 (2013.01); H01L 29/4236 (2013.01); H01L 29/4966 (2013.01); H01L 29/66621 (2013.01); H01L 29/66666 (2013.01); H01L 29/78 (2013.01); H01L 29/7827 (2013.01); H01L 43/12 (2013.01); H01L 45/16 (2013.01); H01L 21/26586 (2013.01); H01L 21/28114 (2013.01); H01L 27/10805 (2013.01); H01L 27/10861 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01);
Abstract

A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

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