IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10811210 B1

PDFFull Text
Date of Patent:
Oct. 20, 2020

Filed:

Oct. 14, 2019

Multilayer printed circuit board via hole registration and accuracy

Applicant:

Sanmina Corporation, San Jose, CA (US);

Inventors:

Shinichi Iketani, Sunnyvale, CA (US);

Douglas Ward Thomas, Pacific Grove, CA (US);

Assignee:

Sanmina Corporation, San Jose, CA (US);

Attorneys:

Loza & Loza, LLP

Julio M. Loza

Primary Examiner:

Timothy J Thompson

Assistant Examiner:

Michael F McAllister

Int. Cl.
CPC ...
G06K 9/62 (2006.01); G11C 15/00 (2006.01); G11C 17/10 (2006.01); G11C 15/04 (2006.01); H01H 85/12 (2006.01); H01H 85/00 (2006.01); H01H 85/143 (2006.01); H05K 3/46 (2006.01); H01H 85/055 (2006.01); H01H 85/20 (2006.01); H01H 85/30 (2006.01); H01H 85/56 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 3/00 (2006.01); H05K 3/10 (2006.01); H05K 3/40 (2006.01); H01H 85/06 (2006.01); H01H 1/58 (2006.01); H01H 85/02 (2006.01); H05K 3/06 (2006.01);
U.S. Cl.
CPC ...
H01H 85/12 (2013.01); H01H 85/0013 (2013.01); H01H 85/055 (2013.01); H01H 85/143 (2013.01); H01H 85/20 (2013.01); H01H 85/306 (2013.01); H01H 85/56 (2013.01); H05K 1/115 (2013.01); H05K 1/144 (2013.01); H05K 3/0047 (2013.01); H05K 3/108 (2013.01); H05K 3/4076 (2013.01); H05K 3/462 (2013.01); H05K 3/4623 (2013.01); H05K 3/4638 (2013.01); H01H 85/06 (2013.01); H01H 2001/5877 (2013.01); H01H 2085/025 (2013.01); H01H 2085/0555 (2013.01); H05K 3/06 (2013.01); H05K 2201/0338 (2013.01); H05K 2201/041 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/09536 (2013.01); H05K 2203/1438 (2013.01); H05K 2203/166 (2013.01); Y10T 29/49165 (2015.01);
Abstract

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

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