The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Jan. 15, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Harsh N. Patel, Clifton Park, NY (US);

Bipul C. Paul, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 13/00 (2006.01); H01L 27/092 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01); H01L 23/528 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 43/02 (2006.01); H01F 10/32 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1657 (2013.01); G11C 11/1655 (2013.01); G11C 11/1675 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); H01L 21/823871 (2013.01); H01L 23/5286 (2013.01); H01L 27/0924 (2013.01); H01L 27/222 (2013.01); H01L 27/2463 (2013.01); H01L 29/42392 (2013.01); G11C 2013/009 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01L 43/02 (2013.01);
Abstract

Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.


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