The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Jun. 05, 2015
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Brent Buchanan, Fort Collins, CO (US);

Ning Ge, Palo Alto, CA (US);

Richard James Auletta, Ft. Collins, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/24 (2006.01); G11C 29/50 (2006.01); G11C 13/00 (2006.01); G11C 5/06 (2006.01); H02H 1/00 (2006.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
G11C 7/24 (2013.01); G11C 5/06 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0059 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 29/50 (2013.01); H02H 1/0061 (2013.01); H02H 9/046 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0078 (2013.01); G11C 2029/5002 (2013.01);
Abstract

In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.


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