The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Feb. 27, 2018
Applicant:

Shanghai Avic Optoelectronics Co., Ltd., Shanghai, CN;

Inventors:

Chang Su, Shanghai, CN;

Huijun Jin, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H01L 27/12 (2006.01); G09G 3/36 (2006.01); G09G 3/3225 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); H01L 27/1229 (2013.01); H01L 27/1233 (2013.01); H01L 27/1285 (2013.01); G09G 3/3225 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0214 (2013.01);
Abstract

An array substrate, a display panel and a display device are provided. The array substrate has a display area including display transistors and gate lines, and a non-display area surrounding the display area and including a gate driving circuit electrically connected to the gate lines. A display transistor includes a display active layer comprising amorphous silicon. The gate driving circuit includes stages of shift registers. A shift register includes a plurality of shift register transistors, a gate signal output terminal, and at least one bootstrap point. The shift register transistors in the shift register include at least one gate output transistor, and the at least one gate output transistor includes a gate electrode electrically connected to the at least one bootstrap point, a first electrode electrically connected to the gate signal output terminal, and a gate output active layer comprising polysilicon.


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