The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Dec. 27, 2016
Applicant:

Beijing Deephi Intelligence Technology Co., Ltd., Beijing, CN;

Inventors:

Dongliang Xie, Beijing, CN;

Song Han, Beijing, CN;

Yi Shan, Beijing, CN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/04 (2006.01); G06N 3/063 (2006.01); G06N 3/08 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01);
U.S. Cl.
CPC ...
G06N 3/0445 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06N 3/063 (2013.01); G06N 3/082 (2013.01); G06F 2207/4824 (2013.01);
Abstract

The present technical disclosure relates to artificial neural networks, e.g., gated recurrent unit (GRU). In particular, the present technical disclosure relates to how to implement a hardware accelerator for compressed GRU based on an embedded FPGA. Specifically, it proposes an overall design processing method of matrix decoding, matrix-vector multiplication, vector accumulation and activation function. In another aspect, the present technical disclosure proposes an overall hardware design to implement and accelerate the above process.


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