The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10808333 B1

Date of Patent:

Oct. 20, 2020

Filed:

Jan. 08, 2019

Method and apparatus for performing layout designs using stem cells

Applicant:

Totic Technology Inc., Morgan Hill, CA (US);

Inventors:

Choshu Ito, San Mateo, CA (US);

Dan Bui, Sunnyvale, CA (US);

Assignee:

Totic Technology Inc., Morgan Hill, CA (US);

Attorney:

Blue Capital Law Firm, P.C.

Primary Examiner:

Suchin Parihar

Int. Cl.

CPC ...

G06F 30/00 (2020.01); C40B 40/02 (2006.01); C12N 5/0735 (2010.01); G06F 30/36 (2020.01); G06F 30/39 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/11 (2006.01); H01L 27/118 (2006.01);

U.S. Cl.

CPC ...

C40B 40/02 (2013.01); C12N 5/0606 (2013.01); G06F 30/327 (2020.01); G06F 30/36 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/1104 (2013.01); H01L 27/11807 (2013.01);

Abstract

A method and system for designing an integrated circuit layout are disclosed. In one embodiment, the method includes generating a stem cell library with stem cell layouts, wherein each stem cell layout includes an analog core area where a device element resides, and abutment boundaries on left, right, top, and bottom sides of the analog core area. The method also includes mapping device elements in a schematic netlist to the stem cell layouts in the stem cell library. In addition, the method includes placing and routing the mapped device elements to optimize a layout for the schematic netlist.

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