The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Sep. 23, 2019
Applicant:

Mediatek Singapore Pte. Ltd., Singapore, SG;

Inventors:

Henry Arnold Park, San Jose, CA (US);

Tamer Mohammed Ali, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/74 (2006.01); H03M 1/12 (2006.01); H03K 19/0185 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03M 1/74 (2013.01); H03K 19/00346 (2013.01); H03K 19/018521 (2013.01); H03M 1/1205 (2013.01); H03M 1/1295 (2013.01);
Abstract

System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.


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