The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Jun. 25, 2018
Applicant:
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Inventors:
Paul Penzes, Irvine, CA (US);
Mark Fullerton, Austin, TX (US);
Assignee:
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED, Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/26 (2006.01); H03L 7/08 (2006.01); H03K 3/03 (2006.01); H03K 3/037 (2006.01); H03K 19/01 (2006.01); G06F 12/14 (2006.01); G06F 21/44 (2013.01); H03K 5/133 (2014.01); H03L 7/097 (2006.01); H03L 7/099 (2006.01); G06F 1/3203 (2019.01); G06F 1/3228 (2019.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); G06F 1/32 (2013.01); G06F 12/14 (2013.01); G06F 21/44 (2013.01); H03K 3/037 (2013.01); H03K 3/0315 (2013.01); H03K 3/0375 (2013.01); H03K 5/133 (2013.01); H03K 19/01 (2013.01); H03L 7/097 (2013.01); H03L 7/0997 (2013.01); G06F 1/26 (2013.01); G06F 1/3203 (2013.01); G06F 1/3228 (2013.01); H01L 2924/0002 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00026 (2013.01); H03K 2005/00058 (2013.01);
Abstract
Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.