Double compression avoidance

Abstract

The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.