The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Jan. 25, 2019
Applicant:
Integrated Device Technology, Inc., San Jose, CA (US);
Inventors:
Samet Zihir, San Diego, CA (US);
Himanshu Khatri, San Diego, CA (US);
Tumay Kanar, San Diego, CA (US);
Assignee:
Integrated Device Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03F 1/08 (2006.01); H03F 3/24 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 1/083 (2013.01); H03F 1/0216 (2013.01); H03F 1/0261 (2013.01); H03F 3/245 (2013.01);
Abstract
An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.
Quick Actions:
Zihir, Samet. (2020). Power amplifier bias network implementation for improving linearity for wideband modulated signals (U.S. Patent No. 10804858). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10804858
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile