The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Mar. 27, 2019
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Daniel J. Black, Tempe, AZ (US);

Antoine D. Fifield, Mesa, AZ (US);

Brian A. Miller, Gilbert, AZ (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); G11C 27/02 (2006.01); H03F 3/45 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
H03F 1/02 (2013.01); G01R 19/0023 (2013.01); G11C 27/026 (2013.01); H03F 3/45 (2013.01); H03F 2203/45151 (2013.01); H03F 2203/45156 (2013.01); H03F 2203/45526 (2013.01);
Abstract

Described herein are systems and methods that reduce settling time in amplifier circuits, such as voltage sense amplifiers (VSA) or current sense amplifiers (CSA) circuits, that comprise a feedback path. When the feedback path is interrupted via a switch, a CSA circuit switches to open loop. A sample-and-hold circuit holds the output voltage of the amplifier, such that when a load is connected to the CSA circuit, the open loop settling time, which is shorter than the closed loop settling time, is allowed to pass before the CSA output voltage is measured, thereby, advantageously preventing any potential disturbance present at the CSA output from being fed back to the CSA input.


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