The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Jan. 16, 2017
Applicant:

Rohm Co., Ltd., Kyoto-shi, Kyoto, JP;

Inventors:

Minoru Nakagawa, Kyoto, JP;

Seigo Mori, Kyoto, JP;

Takui Sakaguchi, Kyoto, JP;

Masatoshi Aketa, Kyoto, JP;

Yuki Nakano, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/1608 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01);
Abstract

A semiconductor deviceincludes a trench gate structureformed in a surface layer portion of a first principal surface of a semiconductor layer. A source regionand a well regionare formed in a surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure. The well regionis formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region. A channel is formed along the trench gate structurein a portion of the well region. A multilayer regionis formed in a region between the trench gate structureand the source regionin the semiconductor layer. The multilayer regionhas a p type impurity regionformed in the surface layer portion of the first principal surface of the semiconductor layer and an n type impurity regionformed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region


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