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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10804275 B1

PDFFull Text
Date of Patent:
Oct. 13, 2020

Filed:

Nov. 26, 2018

Memory array comprising memory cells of z2-fet type

Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Hassan El Dirani, Grenoble, FR;

Thomas Bedecarrats, Saint Martin d'Heres, FR;

Philippe Galy, Le Touvet, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:

Crowe & Dunlevy

Primary Examiner:

Hrayr A Sayadian

Int. Cl.
CPC ...
H01L 27/108 (2006.01); G11C 11/39 (2006.01); H01L 27/102 (2006.01); H01L 29/74 (2006.01); G11C 11/402 (2006.01); G11C 11/409 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10802 (2013.01); G11C 11/39 (2013.01); G11C 11/409 (2013.01); G11C 11/4023 (2013.01); H01L 27/1027 (2013.01); H01L 27/10844 (2013.01); H01L 27/10897 (2013.01); H01L 29/74 (2013.01);
Abstract

A memory array includes memory cells of Z-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.

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El Dirani, Hassan. (2020). Memory array comprising memory cells of z2-fet type (U.S. Patent No. 10804275). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10804275

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