The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Feb. 20, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yeong-Kwon Ko, Suwon-si, KR;

Jun-Yeong Heo, Suwon-si, KR;

Un-Byoung Kang, Hwaseong-si, KR;

Ja-Yeon Lee, Cheonan-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/04 (2014.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06586 (2013.01);
Abstract

A semiconductor package includes a package substrate, a first semiconductor device on an upper surface of the package substrate, a second semiconductor device on an upper surface of the first semiconductor device, a first connection bump attached to a lower surface of the package substrate, a second connection bump interposed between and electrically connected to the package substrate and the first semiconductor device, and a third connection bump interposed between and electrically connected to the first semiconductor device and the second semiconductor device. The first semiconductor device has an edge and a step at the edge.


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