The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Dec. 14, 2018
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Min Kyu Kang, Seoul, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 27/115 (2017.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/33 (2013.01); H01L 24/49 (2013.01); H01L 25/0657 (2013.01); H01L 27/115 (2013.01); H01L 2224/02372 (2013.01);
Abstract
A semiconductor package includes a package substrate, a first chip stack, a second chip stack, and a supporting block. The first chip stack includes first semiconductor chips stacked on the package substrate to be offset in a first direction, and the second chip stack includes second semiconductor chips stacked on the first chip stack to be offset in a second direction. The supporting block includes a through via structure. The second chip stack is supported by the first chip stack and the supporting block.