The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Dec. 06, 2017
Applicant:
Institut Vedecom, Versailles, FR;
Inventor:
Friedbald Kiel, Fontainebleau, FR;
Assignee:
INSTITUT VEDECOM, Versailles, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/473 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 23/373 (2013.01); H01L 23/49838 (2013.01); H01L 23/5389 (2013.01); H01L 25/18 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 2224/2518 (2013.01);
Abstract
The method for producing a preform integrating at least one electronic chip included between insulating and/or conductive laminated internal layers; mechanically securing metal bus-bar segments at given spaced-apart positions on opposing upper and lower faces of the preform, using dielectric portions of a resin prepreg; and for each of the upper and lower opposing faces, electrodepositing a metal layer in order to interconnect bus-bar segments secured to the face in question and an electrode of the electronic chip, thereby forming an electronic power circuit comprising bus-bars forming heat sinks.