The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Mar. 06, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Masashi Yoshida, Yokohama, JP;

Naofumi Abiko, Kawasaki, JP;

Yoshikazu Harada, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); H01L 27/1157 (2017.01); G11C 11/56 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/3459 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0475 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell array; a plurality of bit lines respectively connected to memory cells; a word line commonly connected to the memory cells; and a control circuit. The control circuit programs a first memory cell of a first state and a second memory cell of a second state by using a first program pulse. The control circuit applies a first voltage to a first bit line connected to the first memory cell, and applies a second voltage lower than the first voltage to a second bit line connected to the second memory cell at a first time within a first period during which the first program pulse is applied. The control circuit applies the second voltage to the first and second bit lines at a second time within the first period.


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