The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Apr. 11, 2018
Fanuc Corporation, Yamanashi, JP;
Hitoshi Izumi, Yamanashi, JP;
Kenichiro Kurihara, Yamanashi, JP;
FANUC CORPORATION, Yamanashi, JP;
Abstract
Provided are a circuit configuration optimization apparatus and a machine learning device capable of reducing the occurrence frequency of a malfunction based on one of the current position and the current time of a FPGA device. The circuit configuration optimization apparatus includes: a state data acquisition section that acquires at least one of a current position and current time of the FPGA device as state data; and a circuit configuration determination section that determines a circuit configuration of the FPGA device based on the state data acquired by the state data acquisition section, and outputs a command value for reconfiguring the determined circuit configuration on the FPGA device.